Publications

International journal publications

  1. Marchand, C.; Bossuet, L.; Mureddu, U.; Bochard, N; Cherkaoui, A; Fischer, V, Implementation and characterization of a physical unclonable function for IoT: a case study with the TERO-PUF, in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, May 2017, vol.PP, no.99, doi: 10.1109/TCAD.2017.2702607
  2. Marchand, C.; Bossuet, L.; Gaj, K., Area-oriented comparison of lightweight crypto-hardware on FPGAs, International journal of Circuit Theory and Applications, Wiley, Special issue on Lightweight hardware cryptosystem, February 2017, doi: 10.1002/cta.2288
  3. Cherkaoui, A.; Bossuet, L.; Marchand, C., Design, Evaluation and Optimization of Physical Unclonable Functions based on Transient Effect Ring Oscillators, IEEE Transaction on information forensic and security, February 2016. doi: 10.1109/TIFS.2016.2524666
  4. Jung, E.; Bossuet, L.; Choi, S.; Marchand, C.; Identification of IP control units by state encoding and side channel verification, Microprocessors and Microsystems, February 2016. doi: http://dx.doi.org/10.1016/j.micpro.2016.02.019
  5. Marchand, C. ; Francq, J., Low level implementation and side channel detection of stealthy hardware trojans on FPGAs, IET Computer & Digital Techniques, Special issue on Hardware Security, 2014. doi :10.1049/iet-cdt.2014.0034, pdf

Book chapter

  1. Marchand, C.; Bossuet, L.; Gaj, K., Ultra-Lightweight Implementation in Area of Block Ciphers, Foundations of Hardware IP Protection, Springer, Chapter 9, January 2017, doi: 10.1007/978-3-319-50380-6_9
  2. Bossuet, L.; C. Marchand, C., Side Channel Analysis for IP Protection, Foundations of Hardware IP Protection, Springer, Chapter5, January 2017, doi: 10.1007/978-3-319-50380-6_5

International conferences

  1. Marchand, C.; Bossuet, L.; Cherkaoui, A., Design and characterization of the TERO-PUF on SRAM FPGAs., In proceeding of the IEEE Computer Society Annual Symposium on VLSI, (ISVLSI 2016), July 2016. doi: 10.1109/ISVLSI.2016.18
  2. Marchand, C. ; Bossuet, L.; Cherkaoui, A., Enhanced TERO-PUF implementation and characterization on FPGAs, In Proceedings of the 24th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA 2016). (Poster) doi: 10.1145/2847263.2847298
  3. Jung, E., Marchand, C. ; Bossuet, L., Identification of Embedded Control Units by State Encoding and Power Consumption Analysis., Proceedings of the 30th ACM/SIGAPP Symposium on Applied Computing, (SAC 2015). (Poster) doi: 10.1145/2695664.2695963
  4. Marchand, C. ; Bossuet, L. Jung, E., IP watermark verification based on powerconsumption analysis, Proceedings of 27th International Systems-on-Chip Conference, (SOCC 2014), doi: 10.1109/SOCC.2014.6948949, pdf

Publication without proceedings

  1. Bochard N., Marchand C., Petura O., Bossuet L., Fischer, V., Evariste III: A new multi-FPGA system for fair benchmarking of hardware dependent cryptographic primitives, in Proceedings of Cryptographic Hardware and Embedded Systems, CHES 2015. (Poster)
  2. Marchand, C. ; Bossuet, L., Counterfeits detection and IP Protection by using FSM watermarking and Side Channel Verification, Workshop Phisic 2015
  3. Marchand, C. ; Cherkaoui, A. ; Bossuet, L., Enhanced TERO-PUF design and characterization with FPGA, Workshop on Trustworthy Manufacturing and Utilization of Secure Devices (TRUDEVICE)
  4. Marchand, C. ; Bossuet, L. ; Jung, E., Analyse de la consommation de puissance appliquée à la vérification du marquage d’IP, Journée Sécurité Numérique, Décembre 2014 slides pdf
  5. Marchand, C. ; Bossuet, L., Correlation analysis of the power consumption applied to IP watermark verification, GdR SoC-SiP 2014

Last update : 07/10/2017>